F-Tile Interlaken Intel FPGA IP Design Example

Isikhokelo sokuQalisa ngokukhawuleza

I-F-Tile Interlaken Intel® FPGA IP core inikeza i-testbench yokulinganisa. Uyilo lwehardware example exhasa ukuhlanganiswa kunye novavanyo lwehardware iya kufumaneka kwi-Intel Quartus® Prime Pro Edition software version 21.4. Xa uvelisa uyilo exampLe, umhleli weparameter yenza ngokuzenzekelayo i files iyimfuneko ukulinganisa, ukuqokelela, kunye nokuvavanya uyilo.
I-testbench kunye noyilo example ixhasa i-NRZ kunye ne-PAM4 imo yezixhobo ze-F-tile. I-F-Tile Interlaken Intel FPGA IP engundoqo yenza i-design exampLes kwezi zilandelayo zixhaswayo zendibaniselwano yenani leendlela kunye namazinga edatha.

I-IP exhaswayo Udibaniso lweNani leMizila kunye neeReyithi zeDatha
Ezi ndibaniselwano zilandelayo zixhaswa kwi-Intel Quartus Prime Pro Edition software version 21.3. Zonke ezinye iindibaniselwano ziya kuxhaswa kuguqulelo lwexesha elizayo lwe-Intel Quartus Prime Pro Edition.

Inani leeNdlela	Umlinganiselo weNdlela (Gbps)
	6.25	10.3125	12.5	25.78125	53.125
4	Ewe	-	Ewe	Ewe	-
6	-	-	-	Ewe	Ewe
8	-	-	Ewe	Ewe	-
10	-	-	Ewe	Ewe	-
12	-	Ewe	Ewe	Ewe	-

Umzobo 1.Amanyathelo oPhuhliso kuYilo Example

Phawula: Ukuhlanganiswa kweHardware kunye noVavanyo kuya kufumaneka kwi-Intel Quartus Prime Pro Edition software version 21.4.
I-F-Tile Interlaken Intel FPGA IP core uyilo example ixhasa ezi mpawu zilandelayo:

• I-TX yangaphakathi ukuya kwimowudi yeserial loopback ye-RX
• Yenza iipakethi zobungakanani obuzinzileyo ngokuzenzekelayo
• Ipakethe esisiseko yokujonga amandla
• Ukukwazi ukusebenzisa iSystem Console ukusetha kwakhona uyilo ngenjongo yokuvavanya kwakhona

Umzobo 2.I-High-level Block Diagram

Ulwazi olunxulumeneyo

• F-Tile Interlaken Intel FPGA IP User Guide
• F-Tile Interlaken Intel FPGA IP amanqaku okuKhupha

IiMfuno zeHardware kunye neSoftware

Ukuvavanya i-example uyilo, sebenzisa ihardware elandelayo kunye nesoftware:

• Intel Quartus Prime Pro Edition software version 21.3
• Inkqubo yeConsole
• Isifanisi esixhaswayo:
  • Isishwankathelo* VCS*
  • Iisinopsy VCS MX
  • Siemens* EDA ModelSim* SE okanye Questa*

Phawula:  Inkxaso yehardware yoyilo exampLe iya kufumaneka kwi-Intel Quartus Prime Pro Edition software version 21.4.

Ukuvelisa uYilo

Umzobo 3. Inkqubo

Landela la manyathelo ukwenza uyilo example kunye ne-testbench:

1. Kwisoftware ye-Intel Quartus Prime Pro Edition, cofa File ➤ IWizard yeProjekthi Entsha ukwenza iprojekthi entsha ye-Intel Quartus Prime, okanye ucofe File ➤ Vula iProjekthi yokuvula iprojekthi esele ikho ye-Intel Quartus Prime. Iwizard ikwenza ukuba uchaze isixhobo.
2. Cacisa isixhobo sosapho lwe-Agilex kwaye ukhethe isixhobo esine-F-Tile yoyilo lwakho.
3. KwiKhathalogi ye-IP, fumana kwaye ucofe kabini i-F-Tile Interlaken Intel FPGA IP. Iwindow eNtsha eyahlukileyo ye-IP iyavela.
4. Chaza igama lomgangatho ophezulu ukwenzela ukwahluka kwe-IP yakho. Umhleli weparameter ugcina useto loguqulo lwe IP kwi file igama .ip.
5. Cofa u-Kulungile. Umhleli weparameter uyavela.

Umzobo 4. Eksample Tab yoYilo

6. Kwi-IP ithebhu, khankanya iiparamitha zokwahluka kondoqo we-IP yakho.
7. KwiEksample Yila isithuba, khetha i Ufaniso ukhetho ukuvelisa testbench.
Qaphela: Ukhetho lwe-Synthesis leye-hardware example uyilo, eya kufumaneka kwi-Intel Quartus Prime Pro Edition software version 21.4.
8. KwiFomathi yeHDL eVeliswe, zombini iVerilog kunye neVHDL ukhetho luyafumaneka.
9. Cofa uVelisa Example Design. Khetha Eksample Dizayini kavimba weefayili iwindow iyavela.
10. Ukuba ufuna ukulungisa uyilo example ndlela yolawulo okanye igama elivela kokungagqibekanga okubonisiweyo (ilk_f_0_example_design), khangela kwindlela entsha kwaye uchwetheze uyilo olutsha exampigama lolawulo.
11. Cofa Kulungile.

Phawula: Kwi-F-Tile Interlaken Intel FPGA IP yoyilo exampLe, i-SystemPLL yenziwe ngokuzenzekelayo, kwaye iqhagamshelwe kwi-F-Tile Interlaken Intel FPGA IP core. Indlela yolawulo lweSystemPLL kuyilo example yi:

example_design.test_env_inst.test_dut.dut.pll

I-SystemPLL kuyilo example yabelana ngewotshi efanayo ye-156.26 MHz njengeTransceiver.

Ulwakhiwo lukavimba weefayili

I-F-Tile Interlaken Intel FPGA IP core yenza oku kulandelayo files yoyilo example:
Umzobo 5. Ulwakhiwo lukavimba weefayili

Uluhlu loku-2. Uyilo lwezixhobo zekhompyutha Eksample File Iinkcazelo
Ezi files kwiample_installation_dir>/ilk_f_0_example_design directory.

File Amagama	Inkcazo
example_design.qpf	Iprojekthi ye-Intel Quartus Prime file.
example_design.qsf	Intel Quartus Prime useto lweprojekthi file
example_design.sdc jtag_timing_template.sdc	Isinyanzelo soYilo lwe-Synopsys file. Ungakopa kwaye ulungise uyilo lwakho.
sysconsole_testbench.tcl	Engundoqo file yokufikelela kwiNkqubo yeConsole

Phawula: Inkxaso yehardware yoyilo exampLe iya kufumaneka kwi-Intel Quartus Prime Pro Edition software version 21.4.

Itheyibhile 3. Testbench File Inkcazo

Oku file ikuample_installation_dir>/ilk_f_0_example_design/ umzample_design/rtl ulawulo.

File Igama	Inkcazo
phezulu_tb.sv	Inqanaba eliphezulu testbench file.

Itheyibhile 4. Izikripthi zeTestbench

Ezi files kwiample_installation_dir>/ilk_f_0_example_design/ umzample_design/testbench directory

File Igama	Inkcazo
run_vcs.sh	Iskripthi se-Synopsys VCS sokusebenzisa i-testbench.
run_vcsmx.sh	Iskripthi se-Synopsys VCS MX sokusebenzisa i-testbench.
run_mentor.tcl	I-Siemens EDA ModelSim SE okanye i-Questa script ukuqhuba i-testbench.

Ukulinganisa i-Design Example Testbench

Umzobo 6. Inkqubo

Landela la manyathelo ukulinganisa i-testbench:

1. Kwi-prompt yomyalelo, tshintshela kwi-testbench simulation directory. Indlela yolawulo nguample_installation_dir>/example_design/ testbench.
2. Sebenzisa iskripthi sokulinganisa kwi-simulator exhaswayo oyikhethileyo. Iskripthi siqulunqa kwaye siqhuba i-testbench kwi-simulator. Iskripthi sakho kufuneka sijonge ukuba i-SOP kunye ne-EOP ibala umdlalo emva kokuba ukulinganisa kugqityiwe.

Itheyibhile 5. Amanyathelo okuqhuba ukulinganisa

Isifanisi	Imiyalelo
VCS	Kumgca womyalelo, chwetheza:   sh run_vcs.sh
VCS MX	Kumgca womyalelo, chwetheza:   sh run_vcsmx.sh
ModelSim SE okanye Questa	Kumgca womyalelo, chwetheza:   vsim -yenza run_mentor.tcl Ukuba ukhetha ukulinganisa ngaphandle kokuzisa i-ModelSim GUI, chwetheza:   vsim -c -yenza run_mentor.tcl

3. Hlalutya iziphumo. Ukulinganisa okuphumelelayo kuthumela kwaye kufumane iipakethi, kwaye kubonisa "Uvavanyo LUPASIWE".

I-testbench yoyilo exampugqiba le misebenzi ilandelayo:

• Iqinisekisa i-F-Tile Interlaken Intel FPGA IP engundoqo.
• Iprinta ubume be-PHY.
• Ijonga ungqamaniso lwemetaframe (SYNC_LOCK) kunye negama (ibhloko) imida (WORD_LOCK).
• Ilinda ukuba iindlela ezizimeleyo zitshixiwe kwaye zilungelelaniswe.
• Iqala ukuthumela iipakethi.
• Ijonga iinkcukacha zepakethi:
  • CRC24 iimpazamo
  • Ii-SOPs
  • EOPs

Oku kulandelayo sampimveliso ibonisa impumelelo yovavanyo lokulinganisa:

Ukuqulunqa i-Design Example

1. Qinisekisa example mveliso yoyilo igqityiwe.
2. Kwisoftware ye-Intel Quartus Prime Pro Edition, vula iprojekthi ye-Intel Quartus Primeample_installation_dir>/example_design.qpf>.
3. Kwi-Processing menu, cofa Qala ukuHlanganisa.

Uyilo Eksample Inkcazo

Uyilo example ibonisa ukusebenza kwe-Interlaken IP core.

Uyilo Eksample Components

Exampi-design le idibanisa inkqubo kunye neewotshi zereferensi ze-PLL kunye nezinto ezifunekayo zoyilo. Example uyilo iqwalasela i-IP engundoqo kwimowudi ye-loopback yangaphakathi kwaye ivelise iipakethi kwi-IP engundoqo ye-TX yokudlulisa idatha yomsebenzisi. Undoqo we-IP uthumela ezi pakethi kwindlela yangaphakathi ye-loopback nge-transceiver.
Emva kokuba ummkeli ongundoqo we-IP efumana iipakethi kwindlela ye-loopback, iqhuba iipakethi ze-Interlaken kwaye idlulisele kwi-interface yokudlulisa idatha yomsebenzisi we-RX. Exampi-design ijonga ukuba iipakethi zifunyenwe kwaye zigqithisiwe zihambelana.
Uyilo lwe-F-Tile Interlaken Intel IP example iquka la malungu alandelayo:

1. F-Tile Interlaken Intel FPGA IP core
2. I-Packet Generator kunye nePacket Checker
3. I-F-Tile Reference kunye neNkqubo yePLL Iiwotshi ze-Intel FPGA IP engundoqo

Iimpawu zokunxibelelana

Uluhlu 6. Uyilo Eksample Iimpawu zoNxibelelwano

Igama lePort	Isalathiso	Ububanzi (Amasuntswana)	Inkcazo
mgmt_clk	Igalelo	1	Ungeniso lwewotshi yenkqubo. Amaxesha ewotshi kufuneka abe yi-100 MHz.
pll_ref_clk	Igalelo	1	Iwotshi yereferensi yeTransceiver. Iqhuba i-RX CDR PLL.
rx_pin	Igalelo	Inani leendlela	Umamkeli SEDES iphini yedatha.
tx_pin	Isiphumo	Inani leendlela	Thumela iphini yedatha yeSERDES.
rx_pin_n(1)	Igalelo	Inani leendlela	Umamkeli SEDES iphini yedatha.
tx_pin_n(1)	Isiphumo	Inani leendlela	Thumela iphini yedatha yeSERDES.
mac_clk_pll_ref	Igalelo	1	Lo mqondiso kufuneka uqhutywe yi-PLL kwaye kufuneka usebenzise umthombo ofanayo wewotshi eqhuba i-pll_ref_clk. Lo mqondiso ufumaneka kuphela kwimo ye-PAM4 yokwahluka kwesixhobo.
usr_pb_reset_n	Igalelo	1	Ukusetha kwakhona inkqubo.

(1) Ifumaneka kuphela kwiintlobo ze-PAM4.

Intel Corporation. Onke Amalungelo Agciniwe. I-Intel, ilogo ye-Intel, kunye nezinye iimpawu ze-Intel ziimpawu zorhwebo ze-Intel Corporation okanye iinkampani eziphantsi kwayo. I-Intel iqinisekisa ukusebenza kweFPGA yayo kunye neemveliso zesemiconductor kwiinkcukacha zangoku ngokuhambelana newaranti esemgangathweni ye-Intel, kodwa inelungelo lokwenza utshintsho kuzo naziphi na iimveliso kunye neenkonzo nangaliphi na ixesha ngaphandle kwesaziso. I-Intel ayithathi xanduva okanye ityala elivela kwisicelo okanye ukusetyenziswa kwalo naluphi na ulwazi, imveliso, okanye inkonzo echazwe apha ngaphandle kokuba kuvunyelwene ngokubhaliweyo yi-Intel. Abathengi be-Intel bayacetyiswa ukuba bafumane inguqulelo yamva nje yeenkcazo zesixhobo ngaphambi kokuba baxhomekeke kulo naluphi na ulwazi olupapashiweyo naphambi kokubeka iiodolo zeemveliso okanye iinkonzo.
*Amanye amagama kunye neempawu zingabangwa njengempahla yabanye.

Bhalisa imephu

Phawula:

• Uyilo EksampIdilesi yerejista iqala ngo-0x20** ngelixa idilesi yerejista ye-Interlaken IP engundoqo iqala ngo-0x10**.
• Idilesi yerejista ye-F-tile ye-PHY iqala ngo-0x30** ngelixa idilesi yerejista ye-F-tile ye-FEC iqala ngo-0x40**. Irejista ye-FEC ifumaneka kuphela kwimodi ye-PAM4.
• Ikhowudi yokufikelela: RO—Funda Kuphela, kunye ne-RW—Funda/Bhala.
• Inkqubo console ifunda uyilo example iirejista kwaye ingxelo ubume uvavanyo kwisikrini.

Uluhlu 7. Uyilo Eksample Bhalisa imephu

Offset	Igama	Ukufikelela	Inkcazo
8'h00	Igciniwe
8'h01	Igciniwe
8'h02	Ukusetha kwakhona inkqubo ye-PLL	RO	Amasuntswana alandelayo abonisa inkqubo ye-PLL isicelo sokusetha ngokutsha kwaye wenze ixabiso: • Intwana [0] – sys_pll_rst_req • Intwana [1] – sys_pll_rst_en
8'h03	Indlela ye-RX ilungelelanisiwe	RO	Ibonisa ulungelelwaniso lwendlela ye-RX.
8'h04	WORD itshixiwe	RO	[NUM_LANES–1:0] – Igama (ibhloko) ukuchongwa kwemida.
8'h05	Ungqamaniso lutshixiwe	RO	[NUM_LANES–1:0] – Ungqamaniso lweMetaframe.
8'h06 - 8'h09	CRC32 ubalo lwempazamo	RO	Ibonisa i-CRC32 count yempazamo.
8h0A	CRC24 ubalo lwempazamo	RO	Ibonisa i-CRC24 count yempazamo.
8h0b	Isiginali yokuphuphuma/Ngaphantsi	RO	Amasuntswana alandelayo abonisa: • Bit [3] – TX isiginali yokuqukuqela • Bit [2] – TX isignali yokuphuphuma • Bit [1] – RX isignali yokuphuphuma
8'h0C	Ubalo lwe-SOP	RO	Ibonisa inani le-SOP.
8'h0D	Ukubala kwe-EOP	RO	Ibonisa inani le-EOP
8'h0E	Ubalo lwempazamo	RO	Ibonisa inani leempazamo ezilandelayo: • Ukulahleka kolungelelwaniso lwendlela • Igama elilawulayo elingekho mthethweni • Ipateni yoyilo engekho mthethweni • I-SOP engekho okanye isalathisi se-EOP
8'h0F	send_data_mm_clk	RW	Bhala isi-1 kwibhithi [0] ukwenza isignali yomvelisi.
8'h10	Imposiso yomkhangeli		Ibonisa impazamo yomkhangeli. (Impazamo yedatha ye-SOP, impazamo yenombolo yesitishi, kunye nempazamo yedatha ye-PLD)
8'h11	Isitshixo sePLL yeNkqubo	RO	I-Bit [0] ibonisa isalathiso sokutshixa i-PLL.
8'h14	TX SOP ubalo	RO	Ibonisa inani le-SOP eveliswe yi-packet generator.
8'h15	TX EOP ukubala	RO	Ibonisa inani le-EOP eveliswe yi-packet generator.
8'h16	Ipakethi eqhubekayo	RW	Bhala i-1 ukuya kwibit [0] ukwenza ipakethi eqhubekayo.
iqhubekile...

Offset	Igama	Ukufikelela	Inkcazo
8'h39	Ubalo lwemposiso ye-ECC	RO	Ibonisa inani leempazamo ze-ECC.
8'h40	I-ECC ilungise inani lemposiso	RO	Ibonisa inani leempazamo ezilungisiweyo ze-ECC.
8'h50	ithayile_tx_rst_n	WO	Ukusetwa kwakhona kwethayile kwi-SRC ye-TX.
8'h51	ithayile_rx_rst_n	WO	Ukusetwa kwakhona kwethayile kwi-SRC ye-RX.
8'h52	ithayile_tx_rst_ack_n	RO	Ukusetha kwakhona kwethayile ukuvuma ukusuka kwi-SRC ye-TX.
8'h53	ithayile_rx_rst_ack_n	RO	Ukusetwa kwakhona kwethayile ukuvuma ukusuka kwi-SRC ye-RX.

Lungisa kwakhona

Kwi-F-Tile Interlaken Intel FPGA IP core, uqala ukuseta kwakhona (reset_n=0) kwaye ubambe de i-IP core ibuyisele ukuseta kwakhona ukuvuma (reset_ack_n=0). Emva kokuba ukusetha kwakhona kususiwe (reset_n=1), ukusetwa kwakhona kwemvume kubuyela kwimeko yayo yokuqala.
(reset_ack_n=1). Kuyilo exampLe, irejista ye-rst_ack_sticky ibamba ukusetwa kwakhona kokuvuma kwaye emva koko ibangele ukususwa kokusetha kwakhona (ukusetha kwakhona_n=1). Ungasebenzisa ezinye iindlela ezihambelana neemfuno zakho zoyilo.

Kubalulekile: Kuyo nayiphi na imeko apho uthotho lwangaphakathi lufuneka khona, kufuneka ukhulule i-TX kunye ne-RX ye-F-tile ngokwahlukeneyo ngendlela ethile. Jonga kwisikripthi se-console yenkqubo ngolwazi oluthe vetshe.

Umzobo 7.Setha kwakhona ulandelelwano kwiModi ye-NRZ

Umzobo 8.Setha kwakhona ulandelelwano kwi-PAM4 Mode

F-Tile Interlaken Intel FPGA IP Design Example ULondolozo lweeNkcukacha eziBalulekileyo

Ukuba i-IP core version ayidweliswanga, isikhokelo somsebenzisi senguqulo yangaphambili ye-IP siyasebenza.

Intel Quartus Prime Version	IP Core Version	Isikhokelo somsebenzisi
21.2	2.0.0	F-Tile Interlaken Intel FPGA IP Design Example Isikhokelo somsebenzisi

Imbali yoHlaziyo yoXwebhu lwe-F-Tile Interlaken Intel FPGA IP Design Example Isikhokelo somsebenzisi

Inguqulelo yoXwebhu	Intel Quartus Prime Version	IP Version	Iinguqu
2021.10.04	21.3	3.0.0	• Inkxaso eyongeziweyo yendibaniselwano yereyithi yendlela entsha. Ngolwazi oluthe vetshe, jonga ku Itheyibhile: IiNdibaniselwano eziXhasiweyo ze-IP zeNani leMizila kunye neNqanaba leDatha. • Ukuhlaziya uluhlu lwesilingisi esixhaswayo kwicandelo: IiMfuno zeHardware kunye neSoftware. • Kongezwe iirejista ezintsha zokusetha kwakhona kwicandelo: Bhalisa imephu.
2021.06.21	21.2	2.0.0	Ukukhutshwa kokuqala.

Amaxwebhu / Izibonelelo

intel F-Tile Interlaken Intel FPGA IP Design Example [pdf] Isikhokelo somsebenzisi F-Tile Interlaken Intel FPGA IP Design Example, F-Tile, Interlaken Intel FPGA IP Design Example, Intel FPGA IP Design Example, IP Design Example, Uyilo Eksample

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