intel F-Tile Interlaken FPGA IPDesign Example Isikhokelo somsebenzisi

 

Ihlaziywe kwi-Intel® Quartus® Prime Design Suite: 21.4
IP Version: 3.1.0

1. Isikhokelo sokuQala esiKhawulezayo

I-F-Tile Interlaken Intel® FPGA IP core ibonelela ngebhentshi yokulinganisa yokulinganisa kunye noyilo lwehardware ex.ample exhasa ukuhlanganiswa kunye novavanyo lwehardware. Xa uvelisa uyilo exampLe, umhleli weparameter yenza ngokuzenzekelayo i files iyimfuneko ukulinganisa, ukuqokelela, kunye nokuvavanya uyilo.

I-testbench kunye noyilo example ixhasa i-NRZ kunye ne-PAM4 imo yezixhobo ze-F-tile.
I-F-Tile Interlaken Intel FPGA IP engundoqo yenza i-design exampLes kwezi zilandelayo zixhaswayo zendibaniselwano yenani leendlela kunye namazinga edatha.

Itheyibhile 1. I-IP exhaswayo Udibaniso lweNani leeNdlela kunye neeReyithi zeDatha
Ezi ndibaniselwano zilandelayo zixhaswa kwi-Intel Quartus® Prime Pro Edition software version 21.4. Konke
ezinye iindibaniselwano ziya kuxhaswa kuguqulelo lwexesha elizayo lwe-Intel Quartus Prime Pro Edition.

 

Umzobo 1. Amanyathelo oPhuhliso kuYilo Example

(1) Lo mahluko uxhasa iNdlela yokuJonga ecaleni kwe-Interlaken.
(2) Kuyilo lokucwangciswa kwendlela ye-10, i-F-tile idinga imizila ye-12 ye-TX PMA ukwenzela ukuba i-clocking ye-transceiver edibeneyo yokunciphisa i-channel skew.

*Amanye amagama kunye neempawu zingabangwa njengempahla yabanye.

I-F-Tile Interlaken Intel FPGA IP core uyilo example ixhasa ezi mpawu zilandelayo:

• I-TX yangaphakathi ukuya kwimowudi yeserial loopback ye-RX
• Yenza iipakethi zobungakanani obuzinzileyo ngokuzenzekelayo
• Ipakethe esisiseko yokujonga amandla
• Ukukwazi ukusebenzisa iSystem Console ukusetha kwakhona uyilo ngenjongo yokuvavanya kwakhona

Umzobo 2. Umzobo weBlock yezinga eliphezulu

Ulwazi olunxulumeneyo

• F-Tile Interlaken Intel FPGA IP User Guide
• F-Tile Interlaken Intel FPGA IP amanqaku okuKhupha

1.1. IiMfuno zeHardware kunye neSoftware
Ukuvavanya i-example uyilo, sebenzisa ihardware elandelayo kunye nesoftware:

• Intel Quartus Prime Pro Edition software version 21.4
• Ikhonsoli yeSistim ekhoyo kunye nesoftware ye-Intel Quartus Prime Pro Edition
• Isifanisi esixhaswayo:
  — Iisinopsy* VCS*
  - Iisinopsy VCS MX
  — Siemens* EDA ModelSim* SE okanye Questa*
  -Cadence* Xcelium*
• I-Intel Agilex™ I-Series Transceiver-SoC Development Kit

1.2. Ukuvelisa uYilo
Umzobo 3. Inkqubo

Landela la manyathelo ukwenza uyilo example kunye ne-testbench:

1. Kwisoftware ye-Intel Quartus Prime Pro Edition, cofa File ➤ IWizard yeProjekthi Entsha ukwenza iprojekthi entsha ye-Intel Quartus Prime, okanye ucofe File ➤ Vula iProjekthi yokuvula iprojekthi esele ikho ye-Intel Quartus Prime. Iwizard ikwenza ukuba uchaze isixhobo.
2. Cacisa isixhobo sosapho lwe-Agilex kwaye ukhethe isixhobo esine-F-Tile yoyilo lwakho.
3. KwiKhathalogi ye-IP, fumana kwaye ucofe kabini i-F-Tile Interlaken Intel FPGA IP. Iwindow eNtsha eyahlukileyo ye-IP iyavela.
4. Chaza igama lomgangatho ophezulu ukwenzela ukwahluka kwe-IP yakho. Umhleli weparameter ugcina useto loguqulo lwe IP kwi file igama .ip.
5. Cofa u-Kulungile. Umhleli weparameter uyavela.

Umzobo 4. Eksample Tab yoYilo

6. Kwi-IP ithebhu, khankanya iiparamitha zokwahluka kondoqo we-IP yakho.
7. KwiEksample Yila isithuba, khetha i Ufaniso ukhetho ukuvelisa testbench. Khetha i Synthesis ukhetho ukuvelisa uyilo lwe hardware example. Kufuneka ukhethe enye yeenketho zokulinganisa kunye noHlanganiso ukwenza uyilo lwe example.
8. KwiFomathi yeHDL eVeliswe, zombini iVerilog kunye neVHDL ukhetho luyafumaneka.
9. KwiKhithi yoPhuhliso lweThagethi, khetha i-Agilex I-Series Transceiver-SOC Development Kit.

Qaphela: Xa ukhetha ukhetho lweKit yoPhuhliso, izabelo ze-pin zisetwa ngokwe-Intel Agilex I-Series Transceiver-SoC Development Kit yesixhobo senombolo yesixhobo (AGIB027R31B1E2VR0) kwaye inokwahluka kwisixhobo sakho esikhethiweyo. Ukuba ujonge ukuvavanya uyilo kwihardware kwiPCB eyahlukileyo, khetha Akukho khetho lwekhithi yophuhliso kwaye wenze izabelo zepin ezifanelekileyo kwi .qsf file
10. Cofa uVelisa Example Design. Khetha Eksample Dizayini kavimba weefayili iwindow iyavela.
11. Ukuba ufuna ukulungisa uyilo example ndlela yolawulo okanye igama elivela kokungagqibekanga okubonisiweyo (ilk_f_0_example_design), khangela kwindlela entsha kwaye uchwetheze uyilo olutsha exampigama lolawulo.
12. Cofa Kulungile.

Qaphela: Kwi-F-Tile Interlaken Intel FPGA IP yoyilo exampLe, i-SystemPLL yenziwe ngokuzenzekelayo, kwaye iqhagamshelwe kwi-F-Tile Interlaken Intel FPGA IP core. Indlela yolawulo lweSystemPLL kuyilo example yi:

example_design.test_env_inst.test_dut.dut.pll

I-SystemPLL kuyilo example yabelana ngewotshi efanayo ye-156.26 MHz njengeTransceiver.

1.3. Ulwakhiwo lukavimba weefayili
I-F-Tile Interlaken Intel FPGA IP core yenza oku kulandelayo files yoyilo
example:
Umzobo 5. Ulwakhiwo lukavimba weefayili

Itheyibhile 2. Uyilo lweHardware Example File Iinkcazelo
Ezi files kwiample_installation_dir>/ilk_f_0_example_design directory.

Itheyibhile 3. Testbench File Inkcazo
Oku file ikuample_installation_dir>/ilk_f_0_example_design/example_design/rtl ulawulo.

Itheyibhile 4. Izikripthi zeTestbench
Ezi files kwiample_installation_dir>/ilk_f_0_example_design/example_design/testbench directory.

1.4. Ukulinganisa i-Design Example Testbench
Umzobo 6. Inkqubo

Landela la manyathelo ukulinganisa i-testbench:

1. Kwi-prompt yomyalelo, tshintshela kwi-testbench simulation directory. Indlela yolawulo nguample_installation_dir>/example_design/testbench.
2. Sebenzisa iskripthi sokulinganisa kwi-simulator exhaswayo oyikhethileyo. Iskripthi siqulunqa kwaye siqhuba i-testbench kwi-simulator. Iskripthi sakho kufuneka sijonge ukuba i-SOP kunye ne-EOP ibala umdlalo emva kokuba ukulinganisa kugqityiwe.

Itheyibhile 5. Amanyathelo okuqhuba ukulinganisa

3. Hlalutya iziphumo. Ukulinganisa okuphumelelayo kuthumela kwaye kufumane iipakethi, kwaye kubonisa "Uvavanyo LUPASIWE".
I-testbench yoyilo exampugqiba le misebenzi ilandelayo:

• Iqinisekisa i-F-Tile Interlaken Intel FPGA IP engundoqo.
• Iprinta ubume be-PHY.
• Ijonga ungqamaniso lwemetaframe (SYNC_LOCK) kunye negama (ibhloko) imida
  (ISIXHELO_ZWI).
• Ilinda ukuba iindlela ezizimeleyo zitshixiwe kwaye zilungelelaniswe.
• Iqala ukuthumela iipakethi.
• Ijonga iinkcukacha zepakethi:
  — CRC24 iimpazamo
  - Ii-SOPs
  -EOPs

Oku kulandelayo sampimveliso ibonisa impumelelo yovavanyo lokulinganisa:

Qaphela: Uyilo lwe-Interlaken example testbench yokulinganisa ithumela iipakethi ezili-100 kwaye ifumana iipakethi ezili-100.

Oku kulandelayo sample mveliso ibonisa uvavanyo lokulinganisa oluyimpumelelo lwe-Interlaken Jonga ecaleni kwendlela:

1.5. Ukuqulunqa kunye nokuqwalasela i-Hardware Design Example

1. Qinisekisa example mveliso yoyilo igqityiwe.
2. Kwisoftware ye-Intel Quartus Prime Pro Edition, vula iprojekthi ye-Intel Quartus Primeample_installation_dir>/example_design.qpf>.
3. Kwi Iyaqhuba menu, cofa Qalisa ukuHlanganisa.
4. Emva kokuhlanganiswa ngempumelelo, i.sof file iyafumaneka kulawulo lwakho olukhankanyiweyo.
   Landela la manyathelo ukucwangcisa ihardware exampuyilo kwisixhobo se-Intel Agilex nge-F-tile:
   a. Qhagamshela iKhiti yoPhuhliso kwikhompyuter yenginginya.
   b. Qalisa inkqubo yoLawulo lweClock, eyinxalenye yekhithi yophuhliso. Cwangcisa iifrikhwensi ezintsha zoyilo exampnjengoko kulandelayo:
   • Kwimo ye-NRZ:
   — Si5391 (U18), OUT0: Misela ixabiso le pll_ref_clk(3) ngokwemfuno yakho yoyilo.
   • Kwimo yePAM:
   — Si5391 (U45), OUT1: Misela ixabiso le pll_ref_clk(3) ngokwemfuno yakho yoyilo.
   — Si5391 (U19), OUT1: Misela ixabiso le-mac_pll_ref_clk(3) ngokwemfuno yakho yoyilo. c. Cofa Izixhobo ➤ Umyili weNkqubo ➤ Umiselo lweHardware.
   d. Khetha isixhobo sokucwangcisa. Yongeza i-Intel Agilex I-Series Transceiver-SoC Development Kit.
   e. Qinisekisa ukuba Imowudi isetelwe ku JTAG.
   f. Khetha isixhobo se-Intel Agilex I-Series kwaye ucofe Yongeza Isixhobo. Umdwelisi wenkqubo ubonisa umzobo wonxibelelwano phakathi kwezixhobo ebhodini yakho.
   g. Khangela ibhokisi ye .sof.
   h. Khangela ibhokisi kwi Inkqubo/Lungisa ikholam.
   i. Cofa Qala.

1.6. Ukuvavanya i-Hardware Design Example
Emva kokuba uqokelele i-F-tile Interlaken Intel FPGA IP yoyilo example kwaye uqwalasele isixhobo sakho, ungasebenzisa iNkqubo ye Console ukucwangcisa undoqo we IP kunye neerejista zayo.

Landela la manyathelo ukuzisa iNkqubo yeConsole kwaye uvavanye uyilo lwehardware example:

• Akukho zimpazamo ze-CRC32, CRC24, kunye ne-checker.
• Ii-SOP ezithunyelwayo kunye nee-EOP kufuneka zihambelane nee-SOP ezifunyenweyo kunye nee-EOPs.

Oku kulandelayo sample mveliso ibonisa uvavanyo oluyimpumelelo kwimowudi ye-Interlaken:

Oku kulandelayo sample mveliso ibonisa uvavanyo oluyimpumelelo kwimowudi ye-Interlaken Lookaside:

 

2. Uyilo Eksample Inkcazo

Uyilo example ibonisa ukusebenza kwe-Interlaken IP core.

2.1. Uyilo Eksample Components
Exampi-design le idibanisa inkqubo kunye neewotshi zereferensi ze-PLL kunye nezinto ezifunekayo zoyilo. Example uyilo iqwalasela i-IP engundoqo kwimowudi ye-loopback yangaphakathi kwaye ivelise iipakethi kwi-IP engundoqo ye-TX yokudlulisa idatha yomsebenzisi. Undoqo we-IP uthumela ezi pakethi kwindlela yangaphakathi ye-loopback nge-transceiver.

Emva kokuba ummkeli ongundoqo we-IP efumana iipakethi kwindlela ye-loopback, iqhuba iipakethi ze-Interlaken kwaye idlulisele kwi-interface yokudlulisa idatha yomsebenzisi we-RX. Exampi-design ijonga ukuba iipakethi zifunyenwe kwaye zigqithisiwe zihambelana.

Uyilo lwe-F-Tile Interlaken Intel FPGA IP example iquka la malungu alandelayo:

1. F-Tile Interlaken Intel FPGA IP core
2. I-Packet Generator kunye nePacket Checker
3. I-F-Tile Reference kunye neNkqubo yePLL Iiwotshi ze-Intel FPGA IP engundoqo

2.2. Uyilo Eksample Flow
I-F-Tile Interlaken Intel FPGA IP hardware uyilo example igqibezela la manyathelo alandelayo:

1. Seta kwakhona i-F-tile Interlaken Intel FPGA IP kunye ne-F-Tile.
2. Khupha ukusetha kwakhona kwi-Interlaken IP (ukusetha kwakhona inkqubo) kunye ne-F-tile TX (tile_tx_rst_n).
3. Iqwalasela i-F-tile Interlaken Intel FPGA IP kwimowudi yangaphakathi yokubuyisela umva.
4. Khupha ukusetha kwakhona kwe-F-tile RX (tile_rx_rst_n).
5. Ithumela uthotho lweepakethi ze-Interlaken ezinedatha echazwe kwangaphambili kumthwalo wokuhlawula kwi-TX yomsebenzisi wokudluliselwa kwedatha ye-IP engundoqo.
6. Ijonga iipakethi ezifunyenweyo kwaye ichaze ubume. Umkhangeli wepakethi uqukwe kuyilo lwehardware example ibonelela ngezakhono zokujonga ipakethi esisiseko:
   • Khangela ukuba ulandelelwano lwepakethi ethunyelwayo ichanekile.
   • Ijonga ukuba idatha efunyenweyo iyahambelana na amaxabiso alindelekileyo ngokuqinisekisa ukuba zombini isiqalo sepakethi (SOP) kunye nokuphela kwezibalo zepakethi (EOP) zilungelelaniswa ngelixa idatha ihanjiswa kwaye ifunyanwa.

*Amanye amagama kunye neempawu zingabangwa njengempahla yabanye.

2.3. Iimpawu zokunxibelelana
Uluhlu 6. Uyilo Eksample Iimpawu zoNxibelelwano

2.4. Bhalisa imephu

Phawula:

• Uyilo EksampIdilesi yerejista iqala ngo-0x20** ngelixa idilesi yerejista ye-Interlaken IP engundoqo iqala ngo-0x10**.
• Idilesi yerejista ye-F-tile ye-PHY iqala ngo-0x30** ngelixa idilesi yerejista ye-F-tile ye-FEC iqala ngo-0x40**. Irejista ye-FEC ifumaneka kuphela kwimodi ye-PAM4.
• Ikhowudi yokufikelela: RO—Funda Kuphela, kunye ne-RW—Funda/Bhala.
• Inkqubo console ifunda uyilo example iirejista kwaye ingxelo ubume uvavanyo kwisikrini.

Uluhlu 7. Uyilo Eksample Bhalisa imephu

Uluhlu 8. Uyilo Eksample Bhalisa iMaphu ye-Interlaken Jonga-secaleni uyilo Example
Sebenzisa le mephu yokubhalisa xa uvelisa i-ex yoyiloample nge Yenza i-Interlaken Jonga-ecaleni iparameter ivuliwe.

2.5. Lungisa kwakhona
Kwi-F-Tile Interlaken Intel FPGA IP core, uqala ukuseta kwakhona (reset_n=0) kwaye ubambe de i-IP core ibuyisele ukuseta kwakhona ukuvuma (reset_ack_n=0). Emva kokuba ukusetha kwakhona kususiwe (reset_n=1), ukuseta kwakhona ukuvuma kubuyela kwimeko yayo yokuqala (reset_ack_n=1). Kuyilo exampLe, irejista ye-rst_ack_sticky ibamba ukusetwa kwakhona kokuvuma kwaye emva koko ibangele ukususwa kokusetha kwakhona (ukusetha kwakhona_n=1). Ungasebenzisa ezinye iindlela ezihambelana neemfuno zakho zoyilo.

Kubalulekile: Kuyo nayiphi na imeko apho uthotho lwangaphakathi lufuneka khona, kufuneka ukhulule i-TX kunye ne-RX ye-F-tile ngokwahlukeneyo ngendlela ethile. Jonga kwisikripthi se-console yenkqubo ngolwazi oluthe vetshe.

Umzobo 7. Hlela kwakhona ulandelelwano kwiModi ye-NRZ

Umzobo 8. Hlela kwakhona ulandelelwano kwi-PAM4 Mode

 

3. F-Tile Interlaken Intel FPGA IP Design Example ULondolozo lweeNkcukacha eziBalulekileyo

Ukuba i-IP core version ayidweliswanga, isikhokelo somsebenzisi senguqulo yangaphambili ye-IP siyasebenza.

 

4. Imbali yoHlaziyo yoXwebhu lwe-F-Tile Interlaken Intel FPGA IP Design Example Isikhokelo somsebenzisi

 

Intel Corporation. Onke Amalungelo Agciniwe. I-Intel, ilogo ye-Intel, kunye nezinye iimpawu ze-Intel ziimpawu zorhwebo ze-Intel Corporation okanye iinkampani eziphantsi kwayo. I-Intel iqinisekisa ukusebenza kweFPGA yayo kunye neemveliso zesemiconductor ukuya ngoku
iinkcukacha ngokuhambelana newaranti esemgangathweni ye-Intel, kodwa unelungelo lokwenza utshintsho kuzo naziphi na iimveliso kunye neenkonzo nangaliphi na ixesha ngaphandle kwesaziso. I-Intel ayithathi xanduva okanye ityala elivela kwisicelo okanye ukusetyenziswa kwalo naluphi na ulwazi, imveliso, okanye inkonzo echazwe apha ngaphandle kokuba kuvunyelwene ngokubhaliweyo yi-Intel. Abathengi be-Intel bayacetyiswa ukuba bafumane inguqulelo yamva nje yeenkcazo zesixhobo ngaphambi kokuba baxhomekeke kulo naluphi na ulwazi olupapashiweyo naphambi kokubeka iiodolo zeemveliso okanye iinkonzo.

 

Funda ngakumbi ngale ncwadana & Khuphela iPDF:

Amaxwebhu / Izibonelelo

intel F-Tile Interlaken FPGA IPDesign Example [pdf] Isikhokelo somsebenzisi F-Tile Interlaken FPGA IPDesign Example

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