Intel® FPGA P-Tile Avalon ®
Ukusasaza IP yePCI Express*
Uyilo Eksample Isikhokelo somsebenzisi
Ihlaziywe i-Intel®
IQuartus® Prime Design Suite: 21.3
IP Version: 6.0.0
Isikhokelo somsebenzisi
Uyilo Eksample Inkcazo
1.1. INkcazelo yokuSebenza yeNgeniso/Isiphumo esicwangcisiweyo (PIO) Uyilo Example
Uyilo lwePIO example yenza ugqithiso lwenkumbulo ukusuka kumqhubekekisi wamamkeli ukuya kwisixhobo esijoliswe kuko. Kule exampLe, iprosesa yenginginya icela igama elinye iMemRd kunye ne-emWr
Ii-TLPs.
Uyilo lwePIO example yenza ngokuzenzekelayo i files kuyimfuneko ukulinganisa kunye nokuqokelela kwi-software ye-Intel Prime. Uyilo example iquka uluhlu olubanzi lweeparamitha. Nangona kunjalo, ayiquki zonke iiparameterisation ezinokwenzeka zeP-Tile Hard IP yePCIe.
Lo mzekelo woyiloample iquka la malungu alandelayo:
- I-P-Tile ye-Avalon eveliswayo yokuHamba eNqabileyo ye-IP eyahlukileyo eyahlukileyo (DUT) eneparameters ozichazileyo. Eli candelo liqhuba idatha ye-TLP efunyenwe kwisicelo sePIO
- Icandelo le-PIO Application (APPS), elenza uguqulelo oluyimfuneko phakathi kwe-PCI Express TLPs kunye ne-Avalon-MM elula ibhala kwaye ifundele kwimemori ye-onchip.
- I-on-chip memory (MEM) icandelo. Kuba 1×16 uyilo exampLe, imemori ye-chip iqulathe ibhloko yememori enye ye-16 KB. Kuba 2 × 8 uyilo exampLe, imemori ye-chip iqulathe iibhloko zememori ezimbini ze-16 KB.
- Ukuseta kwakhona ukukhutshwa kwe-IP: Le IP ibambe isiphaluka solawulo ngokusetwa kwakhona de isixhobo singene ngokupheleleyo kwimowudi yomsebenzisi. I-FPGA iqinisekisa imveliso ye-INIT_DONE ukubonisa ukuba isixhobo sikwimowudi yomsebenzisi. Ukukhutshwa kwakhona kwe IP yenza uguqulelo olujikiweyo lwangaphakathi INIT_DONE isignali ukwenza i-nINIT_DONE imveliso onokuyisebenzisa kuyilo lwakho.I-nINIT_DONE isignali iphezulu de isixhobo siphelele singene kwindlela yomsebenzisi. Emva kwee-assers ze-nINIT_DONE (eziphantsi), yonke ingqiqo ikwimo yomsebenzisi kwaye isebenza ngesiqhelo. Ungasebenzisa i-nINIT_DONE isignali kwenye yezi ndlela zilandelayo:
- Ukufaka isango lokusetha kwakhona kwangaphandle okanye kwangaphakathi.
- Ukufaka isango lokusetha kwakhona kwi-transceiver kunye ne-I/O PLLs.
- Ukufaka isango lokubhala luvumela iibhloko zoyilo ezifana neebhloko zememori ezizinzisiweyo, umatshini welizwe, kunye neerejista zeshifti.
- Ukuqhuba ngongqamano kwirejista yokusetha ngokutsha izibuko zongeniso kuyilo lwakho.
Ukulinganisa testbench instantiate PIO uyilo example kunye ne-Root Port BFM ukujongana ne-Endpoint ekujoliswe kuyo.
Intel Corporation. Onke Amalungelo Agciniwe. I-Intel, ilogo ye-Intel, kunye nezinye iimpawu ze-Intel ziimpawu zorhwebo ze-Intel Corporation okanye iinkampani eziphantsi kwayo. I-Intel iqinisekisa ukusebenza kweFPGA yayo kunye neemveliso zesemiconductor kwiinkcukacha zangoku ngokuhambelana newaranti esemgangathweni ye-Intel, kodwa inelungelo lokwenza utshintsho kuzo naziphi na iimveliso kunye neenkonzo nangaliphi na ixesha ngaphandle kwesaziso. I-Intel ayithathi xanduva okanye ityala elivela kwisicelo okanye ukusetyenziswa kwalo naluphi na ulwazi, imveliso, okanye inkonzo echazwe apha ngaphandle kokuba kuvunyelwene ngokubhaliweyo yi-Intel. Abathengi be-Intel bayacetyiswa ukuba bafumane inguqulelo yamva nje yeenkcazo zesixhobo ngaphambi kokuba baxhomekeke kulo naluphi na ulwazi olupapashiweyo naphambi kokubeka iiodolo zeemveliso okanye iinkonzo. *Amanye amagama kunye neempawu zingabangwa njengempahla yabanye.
ISO 9001:2015 ibhalisiwe
Umzobo 1. Umzobo weBlock wePlatform Designer PIO 1 × 16 Design Example Ukulinganisa Testbench
Umzobo 2. Umzobo weBlock wePlatform Designer PIO 2 × 8 Design Example Ukulinganisa Testbench
Inkqubo yovavanyo ibhalela kwaye ifunde umva idatha ukusuka kwindawo enye kwimemori ye-chip. Ithelekisa idatha efundwe kwisiphumo esilindelekileyo. Iingxelo zovavanyo, "Ukulinganisa kuyekile ngenxa yokugqitywa ngempumelelo" ukuba akukho zimpazamo zenzeka. I-P-Tile Avalon
Uyilo lostrimisho example ixhasa olu lungelelwaniso lulandelayo:
- Gen4 x16 Isiphelo
- Gen3 x16 Isiphelo
- Gen4 x8x8 Isiphelo
- Gen3 x8x8 Isiphelo
Phawula: Ukulinganisa testbench kwi PCIe x8x8 PIO uyilo example ilungiselelwe ikhonkco elinye lePCIe x8 nangona uyilo lokwenyani lisebenzisa amakhonkco amabini ePCIe x8.
Phawula: Lo mzekelo woyiloample ixhasa kuphela useto olungagqibekanga kuMhleli weParameter weP-tile Avalon Ukusasaza IP yePCI Express.
Umzobo 3. Imixholo yeNkqubo yoMyili wePlatform yeP-Tile yeAvalon yokusasaza iPCI Express 1×16 PIO Design Example
Umyili wePlatform uvelisa olu yilo ukuya kuthi ga kwiGen4 x16 ezahlukeneyo.
Umzobo 4. Imixholo yeNkqubo yoMyili wePlatform yeP-Tile yeAvalon yokusasaza iPCI Express 2×8 PIO Design Example
Umyili wePlatform uvelisa olu yilo ukuya kuthi ga kwiGen4 x8x8 ezahlukeneyo.
1.2. INkcazelo eSebenzayo yeNgcambu enye ye-I/O Virtualization (SR-IOV) yoYilo Example
Uyilo lwe-SR-IOV example yenza ugqithiso lwenkumbulo ukusuka kumqhubekekisi wamamkeli ukuya kwisixhobo esijoliswe kuko. Ixhasa ukuya kuthi ga kwii-PF ezimbini kunye nama-32 eeVF kwiPF nganye.
Uyilo lwe-SR-IOV example yenza ngokuzenzekelayo i files kuyimfuneko ukulinganisa kunye nokuqokelela kwi-Intel Quartus Prime software. Unakho ukukhuphela uyilo oluhlanganisiweyo ku
i-Intel Stratix® 10 DX Kit yoPhuhliso okanye iKit yoPhuhliso ye-Intel Agilex™.
Lo mzekelo woyiloample iquka la malungu alandelayo:
- Imveliso ye-P-Tile ye-Avalon Streaming (Avalon-ST) IP Endpoint yahluka (DUT) eneparameters ozichazileyo. Eli candelo liqhuba idatha ye-TLP efunyenweyo kwisicelo se-SR-IOV.
- Icandelo le-SR-IOV Application (APPS), elenza uguqulelo oluyimfuneko phakathi kwe-PCI Express TLPs kunye ne-Avalon-ST elula ibhala kwaye ifundele kwimemori ye-chip. Kwicandelo le-SR-IOV APPS, imemori efundwayo ye-TLP iya kuvelisa ukuGqiba ngedatha.
- Kuyilo lwe-SR-IOV example kunye PF ezimbini kunye 32 VFs nganye PF, kukho 66 iindawo memory ukuba uyilo exampndiyakwazi ukufikelela. Ii-PF ezimbini zinokufikelela kwiindawo ezimbini zeememori, ngelixa i-64 VFs (2 x 32) inokufikelela kwiindawo zememori ze-64.
- UkuSeta kwakhona ukukhutshwa kwe-IP.
Ukulinganisa testbench instatiates SR-IOV uyilo example kunye ne-Root Port BFM ukujongana ne-Endpoint ekujoliswe kuyo.
Umzobo 5. I-Block Diagram ye-Platform Designer SR-IOV 1 × 16 Design Example Ukulinganisa Testbench
Umzobo 6. I-Block Diagram ye-Platform Designer SR-IOV 2 × 8 Design Example Ukulinganisa Testbench
Inkqubo yovavanyo ibhalela kwaye ifunde umva idatha ukusuka kwindawo enye kwimemori ye-chip kwi-2 PFs kunye ne-32 VFs kwi-PF nganye. Ithelekisa idatha efundiweyo nelindelekileyo
isiphumo. Iingxelo zovavanyo, "Ukulinganisa kuyekile ngenxa yokugqitywa ngempumelelo" ukuba akukho zimpazamo zenzeka.
Uyilo lwe-SR-IOV example ixhasa olu lungelelwaniso lulandelayo:
- Gen4 x16 Isiphelo
- Gen3 x16 Isiphelo
- Gen4 x8x8 Isiphelo
- Gen3 x8x8 Isiphelo
Umzobo 7. Imixholo yeNkqubo yoMyili wePlatform ye-P-Tile Avalon-ST ene-SR-IOV ye-PCI Express 1× 16 Design Example
Umzobo 8. Imixholo yeNkqubo yoMyili wePlatform ye-P-Tile Avalon-ST ene-SR-IOV ye-PCI Express 2× 8 Design Example
Isikhokelo sokuQalisa ngokukhawuleza
Ukusebenzisa i-Intel Quartus Prime software, unokuvelisa i-I/O ecwangcisiweyo (PIO) yoyilo example ye Intel FPGA P-Tile Avalon-ST Hard IP for PCI Express* IP core. Uyilo oluvelisiweyo example ibonisa iiparameters ozikhankanyayo. I-PIO example idlulisela idata kwiprosesa yomkhosi ukuya kwisixhobo ekujoliswe kuso. Ifanelekile kwizicelo ze-bandwidth ephantsi. Olu luyilo example yenza ngokuzenzekelayo i files kuyimfuneko ukulinganisa kunye nokuqokelela kwi-Intel Quartus Prime software. Ungakhuphela uyilo oluhlanganisiweyo kwiBhodi yoPhuhliso lweFPGA yakho. Ukukhuphela kwi-hardware yesiko, hlaziya i-Intel Quartus Prime Settings File (.qsf) enezikhonkwane ezichanekileyo zezabelo . Umzobo 9. Amanyathelo oPhuhliso kuYilo Example
Intel Corporation. Onke Amalungelo Agciniwe. I-Intel, ilogo ye-Intel, kunye nezinye iimpawu ze-Intel ziimpawu zorhwebo ze-Intel Corporation okanye iinkampani eziphantsi kwayo. I-Intel iqinisekisa ukusebenza kweFPGA yayo kunye neemveliso zesemiconductor kwiinkcukacha zangoku ngokuhambelana newaranti esemgangathweni ye-Intel, kodwa inelungelo lokwenza utshintsho kuzo naziphi na iimveliso kunye neenkonzo nangaliphi na ixesha ngaphandle kwesaziso. I-Intel ayithathi xanduva okanye ityala elivela kwisicelo okanye ukusetyenziswa kwalo naluphi na ulwazi, imveliso, okanye inkonzo echazwe apha ngaphandle kokuba kuvunyelwene ngokubhaliweyo yi-Intel. Abathengi be-Intel bayacetyiswa ukuba bafumane inguqulelo yamva nje yeenkcazo zesixhobo ngaphambi kokuba baxhomekeke kulo naluphi na ulwazi olupapashiweyo naphambi kokubeka iiodolo zeemveliso okanye iinkonzo. *Amanye amagama kunye neempawu zingabangwa njengempahla yabanye.
ISO 9001:2015 ibhalisiwe
2.1. Ulwakhiwo lukavimba weefayili
Umzobo 10. Ulwakhiwo lweNkomfa yoYilo oluDalisiweyo Example
2.2. Ukuvelisa i-Design Example
Umzobo 11. Inkqubo
- Kwisoftware ye-Intel Quartus Prime Pro Edition, yenza iprojekthi entsha (File ➤ Umncedisi Weprojekthi Omtsha).
- Chaza uvimba weefayili, igama kunye neZiko elikwiNqanaba eliphezulu.
- Kudidi lweProjekthi, yamkela ixabiso elisisiseko, iprojekthi engenanto. Cofa Okulandelayo.
- Yongeza Files cofa Okulandelayo.
- KuSapho, isiXhobo kunye noSeto lweBhodi phantsi koSapho, khetha i-Intel Agilex okanye i-Intel Stratix 10.
- Ukuba ukhethe i-Intel Stratix 10 kwinyathelo lokugqibela, khetha i-Stratix 10 DX kwisixhobo sokutsalela phantsi kwimenyu.
- Khetha iSixhobo ekuJoliswe kuso kuyilo lwakho.
- Cofa Gqiba.
- KwiKhathalogi ye-IP fumana kwaye wongeze i-Intel P-Tile Avalon-ST Hard IP yePCI Express.
- Kwibhokisi yencoko yababini eyahlukileyo ye-IP eNtsha, khankanya igama le-IP yakho. Cofa Yenza.
- KwiSetingi zoMgangatho oPhezulu kunye nePCIe* Useto iithebhu, khankanya iiparamitha zokwahluka kwe-IP yakho. Ukuba usebenzisa i SR-IOV uyilo exampLe, yenza la manyathelo alandelayo ukwenza i-SR-IOV:
a. KwiPCIe * Isixhobo ithebhu phantsi kwePCIe * PCI Express / PCI Capabilities ithebhu, khangela ibhokisi Yenza imisebenzi yomzimba emininzi.
b. Kwi-PCIe * Imisebenzi emininzi kunye ne-SR-IOV System Settings tab, khangela ibhokisi Vumela inkxaso ye-SR-IOV kwaye ucacise inani le-PFs kunye ne-VFs. Kuqwalaselo lwe-x8, khangela iibhokisi Yenza imisebenzi yomzimba emininzi kwaye Yenza inkxaso ye-SR-IOV kuzo zombini iithebhu zePCIe0 kunye nePCIe1.
c. Kwi-PCIe* MSI-X ithebhu phantsi kwePCIe* PCI Express / PCI Capabilities ithebhu, yenza i-MSI-X isebenze njengoko kufuneka.
d. Kwi-PCIe* Idilesi yeSiseko seRejista thebhu, yenza ukuba i-BAR0 isebenze kuzo zombini i-PF kunye ne-VF.
e. Ezinye iisetingi zeparameter azixhaswanga koluyilo example. - KwiEksample yoYilo ithebhu, yenza ukhetho olulandelayo:
a. Kuba Eksample Design Files, vula i Ufaniso kunye neenketho zokudityaniswa.
Ukuba awufuni ezi faniso okanye udibaniso files, ukushiya ukhetho(ii) oluhambelanayo lucinyiwe kunciphisa kakhulu i example uyilo ixesha lesizukulwana.
b. KwiFomathi yeHDL eVelweyo, yiVerilog kuphela ekhoyo kukhupho lwangoku.
c. KwiKhithi yoPhuhliso ekujoliswe kuyo, khetha nokuba yi-Intel Stratix 10 DX P-Tile ES1 FPGA Kit yoPhuhliso, i-Intel Stratix 10 DX P-Tile Production FPGA Kit okanye i-Intel Agilex F-Series P-Tile ES0 FPGA Development Kit.
13. Khetha uVelisa Eksample Yila ukuyila uyilo example ukuba ungalinganisa kwaye ukhuphele kwihardware. Ukuba ukhetha enye yeebhodi zophuhliso lwe-P-Tile, isixhobo esikulo bhodi sibhala ngaphezulu isixhobo ebesikhethwe ngaphambili kwiprojekthi ye-Intel Quartus Prime ukuba izixhobo zahlukile. Xa i-prompt ikucela ukuba ukhankanye uluhlu lwe-ex yakhoample uyilo, ungamkela ulawulo olungagqibekanga, ./intel_pcie_ptile_ast_0_example_design, okanye khetha olunye uvimba weefayili.
Umzobo 12. Example Tab yoYilo
- Cofa Gqiba. Ungayigcina i.ip yakho file xa ucelwa, kodwa akufuneki ukuba ukwazi ukusebenzisa i-exampuyilo.
- Vula i-example projekthi yoyilo.
- Qokelela i-example projekthi yoyilo ukwenza i.sof file kuba ex epheleleyoample uyilo. Oku file yinto oyikhuphelayo kwibhodi ukwenza uqinisekiso lwehardware.
- Vala i-ex yakhoample projekthi yoyilo.
Qaphela ukuba awukwazi ukutshintsha i-PCIe pin ulwabiwo kwiprojekthi ye-Intel Quartus Prime. Nangona kunjalo, ukwenza lula umzila wePCB, ungathatha i-advantagi-e yokuguqulwa kwendlela kunye ne-polarity inversion features ezixhaswa yile IP.
2.3. Ukulinganisa i-Design Example
Ukuseta ukulinganisa kubandakanya ukusetyenziswa kweModeli yeBhasi yeBhasi eSebenzayo (BFM) ukusebenzisa i-P-tile Avalon Streaming IP yePCIe (DUT) njengoko kubonisiwe koku kulandelayo.
umfanekiso.
Umzobo 13. Uyilo lwePIO Example Ukulinganisa Testbench
Ukufumana iinkcukacha ezingaphezulu kwi-testbench kunye neemodyuli ezikuyo, jonga kwi-Testbench kwiphepha le-15.
Lo mzobo ulandelayo ubonisa amanyathelo ukulinganisa uyilo example:
Umzobo 14. Inkqubo
- Guqula kwi-testbench simulation directory, / pcie_ed_tb/pcie_ed_tb/sim/ /Isilinganisi.
- Sebenzisa iskripthi sokulinganisa kwisifanisi osikhethileyo. Jonga kwitheyibhile engezantsi.
- Hlalutya iziphumo.
Phawula: I-P-Tile ayixhasi ukulinganisa kwe-PIPE efanayo.
Uluhlu loku-1. Amanyathelo okuqhuba ukulinganisa
| Isifanisi | Uluhlu Lokusebenza | Imiyalelo |
| ModelSim* SE, Siemens* EDA QuestaSim*- Intel FPGA Edition | <example_design>/pcie_ed_tb/ pcie_ed_tb/sim/mentor/ | 1. Biza i-vsim (ngokuchwetheza i-vsim, ezisa ifestile yeconsole apho unokusebenzisa le miyalelo ilandelayo). 2. yenza msim_setup.tcl Qaphela: Kungenjalo, endaweni yokwenza iNyathelo 1 no-2, ungachwetheza: vsim -c -do msim_setup.tcl. 3. ld_debug 4. baleka -konke 5. Ukulinganisa okuyimpumelelo kuphetha ngomyalezo olandelayo, "Ukulinganisa kuyekile ngenxa yokugqitywa ngempumelelo!" |
| VCS* | <example_design>/pcie_ed_tb/ pcie_ed_tb/sim/synopsy/vcs | 1. Chwetheza sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS=”” USER_DEFINED_ELAB_OPTIONS=”-xlrm\ uniq_prior_final” USER_DEFINED_SIM_OPTIONS=” |
| iqhubekile... | ||
| Isifanisi | Uluhlu Lokusebenza | Imiyalelo |
| Qaphela: Umyalelo ongasentla ngumyalelo womgca omnye. 2. Ukulinganisa okuyimpumelelo kuphetha ngomyalezo olandelayo, "Ukulinganisa kuyekile ngenxa yokugqitywa ngempumelelo!" Qaphela: Ukwenza ufaniso kwimo yonxibelelano, sebenzisa la manyathelo alandelayo: (ukuba sele uvelise i-siMV ephunyezwayo kwimo engasebenziyo, cima simv kunye ne simv.diadir) 1. Vula i-vcs_setup.sh file kwaye yongeza inketho yokulungisa iimpazamo kumyalelo weVCS: vcs -debug_access+r 2. Qokelela uyilo example: sh vcs_setup.sh USER_DEFINED_ELAB_OPTIONS=”- xlrm\ uniq_prior_final” SKIP_SIM=1 3. Qala ukulinganisa kwimowudi yonxibelelwano: simv -gui & |
Le testbench ilinganisa ukuya kwi-Gen4 x16 eyahlukileyo.
Ukulinganisa kuxela, "Ukulinganisa kuyekile ngenxa yokugqitywa ngempumelelo" ukuba akukho zimpazamo zenzeka.
2.3.1. Testbench
I-testbench isebenzisa imodyuli yomqhubi wovavanyo, i-altpcietb_bfm_rp_gen4_x16.sv, ukuqalisa ukucwangciswa kunye nokuthengiselana kwememori. Ekuqaliseni, imodyuli yomqhubi wovavanyo ibonisa ulwazi oluvela kwi-Root Port kunye ne-Endpoint Configuration Space iirejista, ukwenzela ukuba udibanise kwiiparameters ozichazileyo usebenzisa iParameter Editor.
Exampuyilo kunye nebhentshi yovavanyo ziveliswa ngokuguquguqukayo ngokusekelwe kuqwalaselo olukhethayo lweP-Tile IP yePCIe. I-testbench isebenzisa iiparameters ozichazayo kuMhleli weParameter kwi-Intel Quartus Prime. Le testbench ilinganisa ukuya kuthi ga kwikhonkco le-× 16 PCI Express usebenzisa i-serial PCI Express interface. Uyilo lwe-testbench luvumela ngaphezulu kwekhonkco elinye le-PCI Express ukuba lifaniswe ngexesha. Lo mfanekiso ulandelayo ubonisa umgangatho ophezulu view yoyilo lwePIO example.
Umzobo 15. Uyilo lwePIO Example Ukulinganisa Testbench
Umgangatho ophezulu we-testbench uqinisekisa ezi modyuli eziphambili zilandelayo:
- altpcietb_bfm_rp_gen4x16.sv —Le yi Root Port PCIe BFM.
//Indlela yolawulo
/intel_pcie_ptile_ast_0_example_design/pcie_ed_tb/ip/
pcie_ed_tb/dut_pcie_tb_ip/intel_pcie_ptile_tbed_ /sim - pcie_ed_dut.ip: Olu luyilo lweNdawo yokuPhelela kunye neeparamitha ozikhankanyayo.
//Indlela yolawulo
/intel_pcie_ptile_ast_0_example_design/ip/pcie_ed - pcie_ed_pio0.ip: Le modyuli kujoliswe kuyo kunye nomqalisi wentengiselwano yoyilo lwePIO example.
//Indlela yolawulo
/intel_pcie_ptile_ast_0_example_design/ip/pcie_ed - pcie_ed_sriov0.ip: Le modyuli ijolise kunye nomqalisi wentengiselwano ye-SR-IOV yoyilo example.
//Indlela yolawulo
/intel_pcie_ptile_ast_0_example_design/ip/pcie_ed
Umzobo 16. SR-IOV Design Example Ukulinganisa Testbench
Ukongeza, i-testbench ineendlela ezenza le misebenzi ilandelayo:
- Ivelisa iwotshi yereferensi yeNqanaba lokuPhelela ngamaxesha afunekayo.
- Ibonelela ngokusetha kwakhona kwe-PCI Express ekuqaleni.
Ukufumana iinkcukacha ezithe vetshe kwi-Root Port BFM, bhekisa kwisahluko se-TestBench se-Intel FPGA P-Tile Avalon yokuhambisa i-IP ye-PCI Express User Guide.
Ulwazi olunxulumeneyo
I-Intel FPGA ye-P-Tile ye-Avalon yokusakaza i-IP ye-PCI Express User Guide
2.3.1.1. Imodyuli yomqhubi wovavanyo
Imodyuli yomqhubi wovavanyo, intel_pcie_ptile_tbed_hwtcl.v, iqinisekisa umgangatho ophezulu we-BFM, altpcietb_bfm_top_rp.v.
I-BFM ekwinqanaba eliphezulu igqibezela le misebenzi ilandelayo:
- Iqinisekisa umqhubi kunye nokubeka iliso.
- Iqinisekisa i-Root Port BFM.
- Iqinisekisa ujongano lweserial.
Imodyuli yoqwalaselo, altpcietb_g3bfm_configure.v, yenza le misebenzi ilandelayo:
- Ukuqwalasela kunye nokwabela ii-BAR.
- Iqwalasela i-Root Port kunye ne-Endpoint.
- Ibonisa isithuba soLungiselelo olubanzi, i-BAR, i-MSI, i-MSI-X, kunye neseto ze-AER.
2.3.1.2. Uyilo lwePIO Example Testbench
Lo mzobo ungezantsi ubonisa i-PIO yoyilo exampUyilo lwenqanaba loyilo lokulinganisa. Iimvavanyo zoyilo lwePIO example zichazwe nge-apps_type_hwtcl ipharamitha emiselwe ku
3. Iimvavanyo eziqhutywa phantsi kweli xabiso leparameter zichazwe kwi-ebfm_cfg_rp_ep_rootport, find_mem_bar kunye ne-downstream_loop.
Umzobo 17. Uyilo lwePIO Example Uyilo loBumo boBumo boBumo
I-testbench iqala ngoqeqesho lwekhonkco kwaye ifikelela kwindawo yoqwalaselo lwe-IP yobalo. Umsebenzi obizwa ngokuba yi-downstream_loop (echazwe kwi-Root Port
PCIe BFM altpcietb_bfm_rp_gen4_x16.sv) emva koko yenze uvavanyo lwekhonkco lwe-PCIe. Olu vavanyo lunala manyathelo alandelayo:
- Khupha umyalelo wokubhala kwimemori ukubhala idword enye yedatha kwimemori ye-chip emva kweNqanawa yokuPhelela.
- Khupha umyalelo wokufunda kwimemori ukuze ufunde umva idatha kwimemori ye-chip.
- Thelekisa idatha efundiweyo kunye nedatha yokubhala. Ukuba ziyahambelana, uvavanyo lubala oku njengePasi.
- Phinda iNyathelo 1, 2 kunye ne-3 ngokuphindaphindiweyo kwe-10.
Ukubhalwa kwenkumbulo yokuqala kwenzeka malunga nama-219 kuthi. Ilandelwa yimemori efundwayo kwi-interface ye-Avalon-ST RX ye-P-tile Hard IP ye-PCIe. I-TLP yokuQeda ibonakala kamsinya emva kokuba isicelo sokufundwa kwememori kwi-interface ye-Avalon-ST TX.
2.3.1.3. SR-IOV Design Example Testbench
Lo mzobo ungezantsi ubonisa SR-IOV uyilo exampUyilo lwenqanaba loyilo lokulinganisa. Iimvavanyo zoyilo lwe-SR-IOV exampzenziwa ngumsebenzi obizwa sriov_test,
echazwa kwi-altpcietb_bfm_cfbp.sv.
Umzobo 18. SR-IOV Design Example Uyilo loBumo boBumo boBumo
I-testbench ye-SR-IOV ixhasa ukuya kuthi ga kwiMisebenzi yoMzimba emibini (PFs) kunye ne-32 Virtual Functions (VFs) ngePF nganye.
I-testbench iqala ngoqeqesho lwekhonkco kwaye ifikelela kwindawo yoqwalaselo lwe-IP yobalo. Emva koko, yenza la manyathelo alandelayo:
- Thumela isicelo sokubhala imemori kwiPF elandelwa sisicelo sokufundwa kwememori ukufunda kwakhona idatha efanayo ukuthelekisa. Ukuba idatha efundwayo ihambelana nedatha yokubhala, kunjalo
iPass. Olu vavanyo lwenziwa ngumsebenzi obizwa ngokuba yi-my_test (echazwe kwi-altpcietb_bfm_cfbp.v). Olu vavanyo luphinda kabini kwiPF nganye. - Thumela isicelo sokubhala imemori kwi-VF elandelwa sisicelo sokufundwa kwememori ukufunda kwakhona idatha efanayo ukuthelekisa. Ukuba idatha efundwayo ihambelana nedatha yokubhala, kunjalo
iPass. Olu vavanyo lwenziwa ngumsebenzi obizwa ngokuba yi-cfbp_target_test (echazwe kwi-altpcietb_bfm_cfbp.v). Olu vavanyo luyaphindwa kwi-VF nganye.
Ukubhalwa kwenkumbulo yokuqala kwenzeka malunga nama-263 kuthi. Ilandelwa yimemori efundwayo kwi-interface ye-Avalon-ST RX ye-PF0 ye-P-tile Hard IP ye-PCIe. I-TLP yokuQeda ibonakala kamsinya emva kokuba isicelo sokufundwa kwememori kwi-interface ye-Avalon-ST TX.
2.4. Ukuqulunqa i-Design Example
- Khangela uye ku /intel_pcie_ptile_ast_0_example_design/ kwaye uvule pcie_ed.qpf.
- Ukuba ukhetha nokuba yiyiphi kwezi zixhobo zophuhliso zimbini zilandelayo, izicwangciso eziyelelene kwiVID zibandakanyiwe kwi .qsf file yoyilo oluvelisiweyo example, kwaye awunyanzelekanga ukuba wongeze ngesandla. Qaphela ukuba olu seto lungqale kwibhodi.
• Ikiti yophuhliso ye-Intel Stratix 10 DX P-Tile ES1 FPGA
• Ikiti ye-Intel Stratix 10 DX P-Tile Production FPGA
• Ikiti yophuhliso lwe-Intel Agilex F-Series P-Tile ES0 FPGA - Kwi-Processing menu, khetha Qala ukuHlanganisa.
2.5. Ukufakela i-Linux Kernel Driver
Ngaphambi kokuba uvavanye i-design exampkwihardware, kufuneka ufake i Linux kernel
umqhubi. Ungasebenzisa lo mqhubi ukwenza olu vavanyo lulandelayo:
• Uvavanyo lwekhonkco lwe-PCIe olwenza i-100 yokubhala nokufunda
• Indawo yenkumbulo DWORD
uyafunda abhale
• Isithuba soLungiselelo lweDWORD iyafunda kwaye ibhale
(1)
Ukongeza, ungasebenzisa umqhubi ukutshintsha ixabiso leeparamitha zilandelayo:
• I-BAR esetyenziswayo
• Isixhobo esikhethiweyo (ngokuchaza iinombolo zebhasi, isixhobo kunye nomsebenzi (BDF) we
isixhobo)
Gqibezela la manyathelo alandelayo ukufaka umqhubi wekernel:
- Layisha ukuya ./software/kernel/linux phantsi kwe example directory yoyilo lokuvelisa.
- Guqula iimvume kufakelo, ukulayisha, kunye nokukhulula files:
$ chmod 777 ufakelo umthwalo - Faka umqhubi:
$ sudo ./fake - Qinisekisa ufakelo lomqhubi:
$ lsmod | igrep intel_fpga_pcie_drv
Iziphumo ezilindelekileyo:
intel_fpga_pcie_drv 17792 0 - Qinisekisa ukuba iLinux iyayiqaphela i-PCIe yoyilo example:
$ lspci -d 1172:000 -v | igrep intel_fpga_pcie_drv
Phawula: Ukuba utshintshile i-ID yoMthengisi, faka i-ID entsha endaweni ye-Intel's
I-ID yomthengisi kulo myalelo.
Iziphumo ezilindelekileyo:
Umqhubi weKernel osebenzayo: intel_fpga_pcie_drv
2.6. Ukuqhuba uYilo Example
Nantsi imisebenzi yovavanyo onokuthi uyenze kwi-P-Tile Avalon-ST PCIe uyilo exampngaphantsi:
- Kuyo yonke le khokelo yomsebenzisi, amagama athi, DWORD kunye neQWORD anentsingiselo efanayo naleyo abanayo kwi-PCI Express Base Specification. Igama linamasuntswana ali-16, i-DWORD ngamasuntswana angama-32, kunye ne-QWORD ngamasuntswana angama-64.
Itheyibhile 2. Uvavanyo lweMisebenzi exhaswa yi-P-Tile Avalon-ST PCIe Design ExampLes
| Imisebenzi | I-BAR efunekayo | Ixhaswa yi-P-Tile Avalon-ST PCIe Design Example |
| 0: Uvavanyo lwekhonkco - i-100 ibhala kwaye ifunde | 0 | Ewe |
| 1: Bhala isithuba senkumbulo | 0 | Ewe |
| 2: Funda indawo yememori | 0 | Ewe |
| 3: Bhala isithuba soqwalaselo | N / A | Ewe |
| 4: Funda indawo yoqwalaselo | N / A | Ewe |
| 5: Guqula IBHA | N / A | Ewe |
| 6: Guqula isixhobo | N / A | Ewe |
| 7: Nika amandla i-SR-IOV | N / A | Ewe (*) |
| 8: Yenza uvavanyo lwekhonkco kuwo wonke umsebenzi owenziwe wasebenza wesixhobo sangoku | N / A | Ewe (*) |
| 9: Yenza i-DMA | N / A | Hayi |
| 10: Yeka inkqubo | N / A | Ewe |
Qaphela: (*) Le misebenzi yovavanyo ifumaneka kuphela xa uyilo lwe-SR-IOV example ikhethiwe.
2.6.1. Ukuqhuba iPIO Design Example
- Yiya ku-./software/user/example phantsi koyilo example directory.
- Qokelela uyilo exampisicelo se:
$ yenza - Yenza uvavanyo:
$ sudo ./intel_fpga_pcie_link_test
Ungaqhuba uvavanyo lwekhonkco lwe-Intel FPGA IP PCIe kwimo yesandla okanye ezenzekelayo. Khetha kwi:
• Kwimowudi ezenzekelayo, usetyenziso luzikhethela isixhobo. Uvavanyo lukhetha isixhobo se-Intel PCIe esine-BDF esezantsi ngokuthelekisa i-ID yoMthengisi.
Uvavanyo lukwakhetha eyona BAR isezantsi ekhoyo.
• Kwimo yesandla, uvavanyo likubuza ngebhasi, isixhobo, kunye nenombolo yokusebenza kunye neBAR.
Kuba Intel Stratix 10 DX okanye Intel Agilex Development Kit, uyakwazi ukumisela
BDF ngokuchwetheza lo myalelo ulandelayo:
$ lspci -d 1172:
4. Nazi imizampLe transcript yeendlela ezizenzekelayo kunye nezandla:
Imowudi ezenzekelayo:
Imo yesandla:
Ulwazi olunxulumeneyo
PCIe Link Umhloli Ngaphezuluview
Sebenzisa i-PCIe Link Inspector ukujonga ikhonkco kwi-Physical, i-Data Link kunye ne-Transaction Layers.
2.6.2. Ukuqhuba i-SR-IOV Design Example
Nanga amanyathelo okuvavanya i-SR-IOV yoyilo exampkwihardware:
- Qhuba uvavanyo lwekhonkco lwe-Intel FPGA IP PCIe ngokwenza i sudo ./
intel_fpga_pcie_link_test umyalelo kwaye ukhethe ukhetho 1:
Khetha isixhobo ngesandla. - Ngenisa i-BDF yomsebenzi obonakalayo apho imisebenzi yenyani yabelwe yona.
- Faka iBAR "0" ukuze uqhubekele kwimenyu yovavanyo.
- Ngenisa ukhetho 7 ukwenza i-SR-IOV kwisixhobo sangoku.
- Ngenisa inani lemisebenzi yenyani ekufuneka yenziwe kwisixhobo sangoku.
- Ngenisa ukhetho 8 ukwenza uvavanyo lwekhonkco kuwo wonke umsebenzi wenyani owenziwe wasebenza owabelwe umsebenzi womzimba. Isicelo sovavanyo lwekhonkco siya kwenza imemori ye-100 ibhala nge-dword enye yedatha nganye kwaye emva koko ifunde idatha yokubuyisela ukujonga. Isicelo siya kuprinta inani lemisebenzi ebonakalayo engaphumelelanga kuvavanyo lwekhonkco ekupheleni kovavanyo.
7. Kwi-terminal entsha, sebenzisa i-lspci –d 1172: | grep -c “Altera” umyalelo wokuqinisekisa ukubalwa kwee-PF kunye nee-VFs. Isiphumo esilindelekileyo sisimbuku senani lemisebenzi yomzimba kunye nenani lemisebenzi ebonakalayo.
I-P-tile ye-Avalon yokusakaza IP ye-PCI Express Design
Example ULondolozo lweeNkcukacha eziBalulekileyo
Intel Corporation. Onke Amalungelo Agciniwe. I-Intel, ilogo ye-Intel, kunye nezinye iimpawu ze-Intel ziimpawu zorhwebo ze-Intel Corporation okanye iinkampani eziphantsi kwayo. I-Intel iqinisekisa ukusebenza kweFPGA yayo kunye neemveliso zesemiconductor kwiinkcukacha zangoku ngokuhambelana newaranti esemgangathweni ye-Intel, kodwa inelungelo lokwenza utshintsho kuzo naziphi na iimveliso kunye neenkonzo nangaliphi na ixesha ngaphandle kwesaziso. I-Intel ayithathi xanduva okanye ityala elivela kwisicelo okanye ukusetyenziswa kwalo naluphi na ulwazi, imveliso, okanye inkonzo echazwe apha ngaphandle kokuba kuvunyelwene ngokubhaliweyo yi-Intel. Abathengi be-Intel bayacetyiswa ukuba bafumane inguqulelo yamva nje yeenkcazo zesixhobo ngaphambi kokuba baxhomekeke kulo naluphi na ulwazi olupapashiweyo naphambi kokubeka iiodolo zeemveliso okanye iinkonzo. *Amanye amagama kunye neempawu zingabangwa njengempahla yabanye.
ISO
9001:2015
Ibhalisiwe
Imbali yoHlaziyo yoXwebhu lwe-Intel P-Tile Avalon
Ukusasaza i-IP enzima yePCIe Design Example Isikhokelo somsebenzisi
| Inguqulelo yoXwebhu | Intel Quartus Prime Version | IP Version | Iinguqu |
| 2021.10.04 | 21.3 | 6.0.0 | Lutshintshe ulungelelwaniso oluxhaswayo lwe-SR-IOV yoyilo example ukusuka ku-Gen3 x16 EP kunye ne-Gen4 x16 EP ukuya kwi-Gen3 x8 EP kunye ne-Gen4 x8 EP kwiNkcazelo eSebenzayo yeNgcambu eyodwa ye-I/O Virtualization (SR-IOV) yoYilo Example candelo. Yongeza inkxaso ye-Intel Stratix 10 DX P-tile yeMveliso yeFPGA yeKhithi yoPhuhliso kuMveliso woYilo Ex.ample candelo. |
| 2021.07.01 | 21.2 | 5.0.0 | Isusiwe iifomati zokulinganisa zePIO kunye ne-SR-IOV yoyilo exampLes ukusuka kwicandelo Ukulinganisa uYilo Eksample. Uhlaziyo lomyalelo wokubonisa iBDF kwicandelo Ukuqhuba iPIO Design Example. |
| 2020.10.05 | 20.3 | 3.1.0 | Isusiwe icandelo loBhaliso ukusukela kuyilo lwe-Avalon Streaming exampLes ayinayo irejista yokulawula. |
| 2020.07.10 | 20.2 | 3.0.0 | Ukongezwa kokulinganisa amaza, iinkcazo zetyala lovavanyo kunye neenkcazo zeziphumo zovavanyo kuyilo lwe-examples. Imiyalelo yokulinganisa eyongeziweyo ye-ModelSim simulator kwi-Simulating Design Example candelo. |
| 2020.05.07 | 20.1 | 2.0.0 | Ihlaziywe isihloko soxwebhu kwi-Intel FPGA P-Tile Avalon yostrimisho lwe-IP yePCI Express Design Example IsiKhokelo soMsebenzisi ukuhlangabezana nezikhokelo ezitsha ezisemthethweni zokuthiywa kwamagama. Kuhlaziywe umyalelo wemowudi esebenzayo yeVCS. |
| 2019.12.16 | 19.4 | 1.1.0 | Kongezwe uyilo lwe-SR-IOV example inkcazo. |
| 2019.11.13 | 19.3 | 1.0.0 | Yongezwe i-Gen4 x8 Endpoint kunye ne-Gen3 x8 Endpoint kuluhlu lolungelelwaniso oluxhaswayo. |
| 2019.05.03 | 19.1.1 | 1.0.0 | Ukukhutshwa kokuqala. |
Intel Corporation. Onke Amalungelo Agciniwe. I-Intel, ilogo ye-Intel, kunye nezinye iimpawu ze-Intel ziimpawu zorhwebo ze-Intel Corporation okanye iinkampani eziphantsi kwayo. I-Intel iqinisekisa ukusebenza kweFPGA yayo kunye neemveliso zesemiconductor kwiinkcukacha zangoku ngokuhambelana newaranti esemgangathweni ye-Intel, kodwa inelungelo lokwenza utshintsho kuzo naziphi na iimveliso kunye neenkonzo nangaliphi na ixesha ngaphandle kwesaziso. I-Intel ayithathi xanduva okanye ityala elivela kwisicelo okanye ukusetyenziswa kwalo naluphi na ulwazi, imveliso, okanye inkonzo echazwe apha ngaphandle kokuba kuvunyelwene ngokubhaliweyo yi-Intel. Abathengi be-Intel bayacetyiswa ukuba bafumane inguqulelo yamva nje yeenkcazo zesixhobo ngaphambi kokuba baxhomekeke kulo naluphi na ulwazi olupapashiweyo naphambi kokubeka iiodolo zeemveliso okanye iinkonzo. *Amanye amagama kunye neempawu zingabangwa njengempahla yabanye.
ISO
9001:2015
Ibhalisiwe
Version Online
Ukuzisa impendulo
I-ID: 683038
UG-20234
Inguqulelo: 2021.10.04
Amaxwebhu / Izibonelelo
 |
intel FPGA P-Tile Avalon Ukusasaza IP yePCI Express Design Example [pdf] Isikhokelo somsebenzisi I-FPGA P-Tile, i-Avalon yokusasaza i-IP yePCI Express Design Example, FPGA P-Tile Avalon Streaming IP for PCI Express Design Example, FPGA P-Tile Avalon Streaming IP |
